Hardware-Algorithm Co-design Enabling Processing-in-Pixel-in-Memory (P2M) for Neuromorphic Vision Sensors

The high volume of data transmission between the edge sensor and the cloud processor leads to energy and throughput bottlenecks for resource-constrained edge devices focused on computer vision. Hence, researchers are investigating different approaches (e.g., near-sensor processing, in-sensor processing, in-pixel processing) by executing computations closer to the sensor to reduce the transmission bandwidth. Specifically, in-pixel processing for neuromorphic vision sensors (e.g., dynamic vision sensors (DVS)) involves incorporating asynchronous multiply-accumulate (MAC) operations within the pixel array, resulting in improved energy efficiency. In a CMOS implementation, low overhead energy-efficient analog MAC accumulates charges on a passive capacitor; however, the capacitor's limited charge retention time affects the algorithmic integration time choices, impacting the algorithmic accuracy, bandwidth, energy, and training efficiency. Consequently, this results in a design trade-off on the hardware aspect-creating a need for a low-leakage compute unit while maintaining the area and energy benefits. In this work, we present a holistic analysis of the hardware-algorithm co-design trade-off based on the limited integration time posed by the hardware and techniques to improve the leakage performance of the in-pixel analog MAC operations.Comment: 6 pages, 4 figures, 1 tabl

A Context-Switching/Dual-Context ROM Augmented RAM using Standard 8T SRAM

The landscape of emerging applications has been continually widening, encompassing various data-intensive applications like artificial intelligence, machine learning, secure encryption, Internet-of-Things, etc. A sustainable approach toward creating dedicated hardware platforms that can cater to multiple applications often requires the underlying hardware to context-switch or support more than one context simultaneously. This paper presents a context-switching and dual-context memory based on the standard 8T SRAM bit-cell. Specifically, we exploit the availability of multi-VT transistors by selectively choosing the read-port transistors of the 8T SRAM cell to be either high-VT or low-VT. The 8T SRAM cell is thus augmented to store ROM data (represented as the VT of the transistors constituting the read-port) while simultaneously storing RAM data. Further, we propose specific sensing methodologies such that the memory array can support RAM-only or ROM-only mode (context-switching (CS) mode) or RAM and ROM mode simultaneously (dual-context (DC) mode). Extensive Monte-Carlo simulations have verified the robustness of our proposed ROM-augmented CS/DC memory on the Globalfoundries 22nm-FDX technology node

Toward High Performance, Programmable Extreme-Edge Intelligence for Neuromorphic Vision Sensors utilizing Magnetic Domain Wall Motion-based MTJ

The desire to empower resource-limited edge devices with computer vision (CV) must overcome the high energy consumption of collecting and processing vast sensory data. To address the challenge, this work proposes an energy-efficient non-von-Neumann in-pixel processing solution for neuromorphic vision sensors employing emerging (X) magnetic domain wall magnetic tunnel junction (MDWMTJ) for the first time, in conjunction with CMOS-based neuromorphic pixels. Our hybrid CMOS+X approach performs in-situ massively parallel asynchronous analog convolution, exhibiting low power consumption and high accuracy across various CV applications by leveraging the non-volatility and programmability of the MDWMTJ. Moreover, our developed device-circuit-algorithm co-design framework captures device constraints (low tunnel-magnetoresistance, low dynamic range) and circuit constraints (non-linearity, process variation, area consideration) based on monte-carlo simulations and device parameters utilizing GF22nm FD-SOI technology. Our experimental results suggest we can achieve an average of 45.3% reduction in backend-processor energy, maintaining similar front-end energy compared to the state-of-the-art and high accuracy of 79.17% and 95.99% on the DVS-CIFAR10 and IBM DVS128-Gesture datasets, respectively.Comment: 11 pages, 7 figures, 2 tabl

COVID-19 Pandemic: A Comparative Prediction Using Machine Learning

Coronavirus Disease 2019 or COVID-19 is an infectious disease which is declared as a pandemic by the World Health Organization (WHO) have a noxious effect on the entire human civilization. Each and every day the number of infected people is going higher and higher and so the death toll. Many of country Italy, UK, USA was affected badly, yet since the identification of the first case, after a certain number of days, the scenario of infection rate has been reduced significantly. However, a country like Bangladesh couldn't keep the infection rate down. A number of algorithms have been proposed to forecast the scenario in terms of the number of infection, recovery and death toll. Here, in this work, we present a comprehensive comparison based on Machine Learning to predict the outbreak of COVID-19 in Bangladesh. Among Several Machine Learning algorithms, here we used Polynomial Regression (PR) and Multilayer Perception (MLP) and Long Short Term Memory (LSTM) algorithm and epidemiological model Susceptible, Infected and Recovered (SIR), projected comparative outcomes

Neuromorphic-P2M: processing-in-pixel-in-memory paradigm for neuromorphic image sensors

Edge devices equipped with computer vision must deal with vast amounts of sensory data with limited computing resources. Hence, researchers have been exploring different energy-efficient solutions such as near-sensor, in-sensor, and in-pixel processing, bringing the computation closer to the sensor. In particular, in-pixel processing embeds the computation capabilities inside the pixel array and achieves high energy efficiency by generating low-level features instead of the raw data stream from CMOS image sensors. Many different in-pixel processing techniques and approaches have been demonstrated on conventional frame-based CMOS imagers; however, the processing-in-pixel approach for neuromorphic vision sensors has not been explored so far. In this work, for the first time, we propose an asynchronous non-von-Neumann analog processing-in-pixel paradigm to perform convolution operations by integrating in-situ multi-bit multi-channel convolution inside the pixel array performing analog multiply and accumulate (MAC) operations that consume significantly less energy than their digital MAC alternative. To make this approach viable, we incorporate the circuit's non-ideality, leakage, and process variations into a novel hardware-algorithm co-design framework that leverages extensive HSpice simulations of our proposed circuit using the GF22nm FD-SOI technology node. We verified our framework on state-of-the-art neuromorphic vision sensor datasets and show that our solution consumes ~2× lower backend-processor energy while maintaining almost similar front-end (sensor) energy on the IBM DVS128-Gesture dataset than the state-of-the-art while maintaining a high test accuracy of 88.36%

Neuromorphic-P2M: Processing-in-Pixel-in-Memory Paradigm for Neuromorphic Image Sensors

Edge devices equipped with computer vision must deal with vast amounts of sensory data with limited computing resources. Hence, researchers have been exploring different energy-efficient solutions such as near-sensor processing, in-sensor processing, and in-pixel processing, bringing the computation closer to the sensor. In particular, in-pixel processing embeds the computation capabilities inside the pixel array and achieves high energy efficiency by generating low-level features instead of the raw data stream from CMOS image sensors. Many different in-pixel processing techniques and approaches have been demonstrated on conventional frame-based CMOS imagers, however, the processing-in-pixel approach for neuromorphic vision sensors has not been explored so far. In this work, we for the first time, propose an asynchronous non-von-Neumann analog processing-in-pixel paradigm to perform convolution operations by integrating in-situ multi-bit multi-channel convolution inside the pixel array performing analog multiply and accumulate (MAC) operations that consume significantly less energy than their digital MAC alternative. To make this approach viable, we incorporate the circuit's non-ideality, leakage, and process variations into a novel hardware-algorithm co-design framework that leverages extensive HSpice simulations of our proposed circuit using the GF22nm FD-SOI technology node. We verified our framework on state-of-the-art neuromorphic vision sensor datasets and show that our solution consumes ~2x lower backend-processor energy while maintaining almost similar front-end (sensor) energy on the IBM DVS128-Gesture dataset than the state-of-the-art while maintaining a high test accuracy of 88.36%.Comment: 17 pages, 11 figures, 2 table

Technology-Circuit-Algorithm Tri-Design for Processing-in-Pixel-in-Memory (P2M)

The massive amounts of data generated by camera sensors motivate data processing inside pixel arrays, i.e., at the extreme-edge. Several critical developments have fueled recent interest in the processing-in-pixel-in-memory paradigm for a wide range of visual machine intelligence tasks, including (1) advances in 3D integration technology to enable complex processing inside each pixel in a 3D integrated manner while maintaining pixel density, (2) analog processing circuit techniques for massively parallel low-energy in-pixel computations, and (3) algorithmic techniques to mitigate non-idealities associated with analog processing through hardware-aware training schemes. This article presents a comprehensive technology-circuit-algorithm landscape that connects technology capabilities, circuit design strategies, and algorithmic optimizations to power, performance, area, bandwidth reduction, and application-level accuracy metrics. We present our results using a comprehensive co-design framework incorporating hardware and algorithmic optimizations for various complex real-life visual intelligence tasks mapped onto our P2M paradigm

Bandgap modulated phosphorene based gate drain underlap double-gate TFET

In this work, a novel bandgap modulated gate drain underlap (BM-GDU) structure of tunnel-FET exhibiting suppressed ambipolar characteristics and steep SS is proposed by applying layer dependent bandgap and electron affinity property of 2-D material Phosphorene. An artificial hetero-junction between the source and channel region is composed of trilayer and bi-layer Phosphorene respectively without any lattice mismatch. BM-GDU TFET exhibits ON-current ∼100 μA/μm, on-off ratio greater than 109 and average subthreshold swing 28.6 mV/decade for a channel length of 20 nm at VDD of 0.4 V due to its low bandgap at source region than the channel region, larger tunneling window and lower carrier effective mass. Gate drain underlap structure yields ∼10 decades ambipolar suppression than conventional homojunction DG TFET. Performance parameters of our BM-GDU TFET by varying channel length are also studied using our developed self-consistent quantum mechanical transport simulator

Blockchain-enable contact tracing for preserving user privacy during COVID-19 outbreak.

Contact tracing has become an indispensable tool of various extensive measures to control the spread of COVID-19 pandemic due to novel coronavirus. This essential tool helps to identify, isolate and quarantine the contacted persons of a COVID-19 patient. However, the existing contact tracing applications developed by various countries, health organizations to trace down the contacts after identifying a COVID-19 patient suffers from several security and privacy concerns. In this work, we have identified those security and privacy issues of several leading contact tracing applications and proposed a blockchain-based framework to overcome the major security and privacy challenges imposed by the applications. We have discussed the security and privacy measures that are achieved by the proposed framework to show the effectiveness against the security and privacy issues raised by the existing mobile contact tracing applications

Assessment of quality of life (QOL) in cancer patients attending oncology unit of a Teaching Hospital in Bangladesh

Abstract Background The quality of life (QoL) of a cancer patient is their perception of their physical, functional, psychological, and social well‐being. QoL is one of the most important factors to consider when treating someone with cancer and during follow‐up. The aim of this study was to understand the state of QoL among cancer patients in Bangladesh and to determine the factors that affect it. Methods This cross‐sectional study was conducted on 210 cancer patients who attended the oncology unit of Delta Medical College & Hospital, Dhaka during the period between 1 May 2022 and 31 August 2022. Data were collected using the Bengali version of the European Organization for Research and Treatment of Cancer (EORTC) questionnaire. Results The study reported a high number of female cancer patients (67.6%), who were married, Muslims by religion, and non‐residents of Dhaka. Breast cancer was more common among women (31.43%), while lung and upper respiratory tract cancer was more prevalent among men (19.05%). The majority of the patients (86.19%) were diagnosed with cancer in the past year. The overall mean score for functional scales was higher for physical functioning (54.92) whereas it was lower for social functioning (38.89). The highest score on the symptom scale was for financial problems (63.02), while the lowest was for diarrhea (33.01). The overall QoL score of cancer patients in the study was 47.98 and it was lower for males (45.71) compared to females (49.10). Conclusions The overall QoL was poor among Bangladeshi cancer patients compared to those in developed countries. A low QoL score was observed for social and emotional functions. Financial difficulty was the main reason behind the lower QoL score on the symptom scale